The present invention relates to the field of computer systems. More specifically, the present invention relates to the field of interconnecting the internal components and peripheral devices of a computer system.
A computer system can be fabricated from a wide variety of individual components and devices which enable it to operate and perform many desirable functions. Some of the internal components of a computer system can include a central processing unit (CPU), a computer readable volatile memory unit (e.g., random access memory, static RAM, dynamic RAM, etc.), a computer readable non-volatile memory unit (e.g., read only memory, programmable ROM, flash memory, EPROM, EEPROM, etc.), a computer readable mass data storage device such as a magnetic or optical disk, modem device, graphics hardware, sound hardware, and the like. Furthermore, some of the peripheral devices of a computer system, which increase its overall functionality, can include a display device, a keyboard for inputting alphanumeric characters, a cursor control device (e.g., mouse), a printer, a scanner, speakers, and the like.
In order for the many internal components and peripheral devices which constitute a computer system to interact and perform desirable functions, they are interconnected by communication buses. These communication buses can be point-to-point buses, which are typically used between two components. Or they can be buses which are shared among several components. The advantages of the shared bus approach is that not as many lines are needed to implement communication between components. Furthermore, the routing conditions of the computer system are reduced.
Typically, all shared bus schemes which allow more than one master to drive cycles on a shared bus, define special arbitration signals which are used between each master and a common control block known as an arbiter. The only purpose of the arbitration signals is to identify which particular master is allowed to drive the shared bus at any particular time, in order to prevent conflicts on the shared bus. The arbitration signals generally consist of a request signal and a grant signal. The request signal is driven by the master to an arbiter unit in order to request permission to drive cycles on the shared bus. The grant signal is driven by the arbiter unit to the master indicating that permission has been granted to start driving cycles on the shared bus. It should be appreciated that for pipelined buses with split address and data bus transactions, there is typically a separate set of signals to perform arbitration for the address and data buses. Therefore, for every master, there could be as many as four extra signals needed to perform arbitration. Apart from the arbitration signals, shared bus schemes define signals to indicate the validity of the cycle being executed on the shared bus. These validity signals consist of signals driven by a master and received by a slave indicating that the master has driven valid signals on the shared bus. Furthermore, these validity signals consist of signals driven by the slave indicating to the master that it has seen the signals driven by the master and they can be driven inactive.
FIGS. 1A and 1B will be discussed in conjunction in order to illustrate a prior art address transaction using the arbitration signals described above. FIG. 1A is a block diagram of a prior art shared bus scheme 100, while FIG. 1B is a corresponding timing diagram 130. On clock 1 of FIG. 1B, master 104 drives a request signal (REQ0_) 112 to an arbiter 102 asking for permission to drive the shared bus (not shown). This request signal 112 is seen by arbiter 102 at clock 2. Since the shared bus is free at that time, arbiter 102 drives a grant signal (GNT0_) 114 to master 104. Upon determining xe2x80x98GRT0_xe2x80x99 signal 114 is active on clock 3, master 104 assumes mastership of the shared bus and drives the shared signals transfer start (TS_) 116 and address (Add) 118. The slave devices on sampling the xe2x80x98TS_xe2x80x99 signal 116 active on clock 4, start the address phase of the cycle. For this example, the address map is split such that one and only one slave responds to any particular cycle. Slave 108, which was selected for execution of this cycle, on clock 8 drives an address acknowledge (AACK_) signal 120 indicating to master 104 that it has seen the cycle and that master 104 can remove xe2x80x98Addxe2x80x99 signal 118. Upon sampling xe2x80x98AACK_xe2x80x99 signal 120 on clock 9, master 104 removes the signals xe2x80x98Addxe2x80x99 118 and xe2x80x98TS_xe2x80x99 116. As such, a prior art address transaction using the arbitration signals has been shown.
There are disadvantages associated with the shared bus schemes of the prior art. The main disadvantage is that the shared bus schemes of the prior art only allow a single address phase to be outstanding at a time over the shared bus. For example, the definition of a prior art shared bus is such that between a master indicating the start of a new cycle and the slave indicating completion of the cycle, the entire shared bus is dedicated for communication between the master and slave. In this manner, the shared bus is not optimally utilized by the master and slave devices connected to it.
Therefore, it would be advantageous to provide a shared bus system to interconnect the internal components and peripheral devices of a computer system which enables multiple outstanding address phases on a shared bus scheme. The present invention provides this advantage.
The present invention includes a shared bus system that interconnects the internal components and peripheral devices of a computer system and enables multiple outstanding address phases on the shared bus scheme. There are three main features of the bus definition of the present embodiment. First, there is reduced signal arbitration within the bus definition. Instead, each master operates as if the shared bus scheme is dedicated for its use. Therefore, all the arbitration is hidden from the circuit blocks connected to the shared bus scheme. Second, all the control signals from the master and slave blocks are point-to-point signals, which are received by a central module. Third, multiple address phases can be simultaneously outstanding over the shared bus scheme. This is accomplished by having the definition of the signals for all slaves such that each slave is to latch an address on the clock signal it detects a valid cycle. In this manner, the shared bus scheme can be optimally utilized. It should be further appreciated that the lack of signal arbitration together with the point-to-point control signals permits circuit blocks to be connected in a wide variety of shared bus schemes while their internal circuitry remains unchanged.
One embodiment in accordance with the present invention is an apparatus for providing communication within a computer system. The apparatus comprises a plurality of modules each having a master port and a slave port for communicating information. Furthermore, the apparatus comprises a secondary bus shared between the plurality of modules for transmitting data between a master port and a slave port of two modules and for transmitting address information between a master port and a slave port of two modules. Additionally, the apparatus comprises a bridge circuit coupled to the plurality of modules and coupled to the secondary bus. The bridge circuit is for individually granting modules of the plurality of modules access to the secondary bus. Moreover, the bridge circuit is also for establishing point-to-point communication paths between a master port and a slave port of two modules of the plurality of modules for communicating control handshake signals there between. The bridge circuit also for establishing and controlling address phases and data phases between modules wherein two address phases can be outstanding at the same time.
These and other advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the drawing figures.